1. Field of the Invention
The present invention relates to a semiconductor memory device and a construction of a portion related to data reading for reading data accurately at high speed. Specifically, the present invention relates to a construction for achieving high-speed data reading in a non-volatile semiconductor memory device.
2. Description of Background Art
A non-volatile semiconductor memory device such as a flash memory is widely used in the field of portable equipments and the like as it can store data in a non-volatile manner. A memory cell structure of the non-volatile semiconductor memory device is roughly divided into a structure utilizing a stacked gate type transistor in which charges are stored in a conductive floating gate formed of polysilicon or the like, and insulating film trap type memory cell structure in which charges are stored in an insulation film such as a nitride film. In either memory cell structure, a threshold voltage of the memory cell transistor is set in accordance with the amount of trapped charges, and the data is stored in accordance with the magnitude of the threshold voltage.
Such a non-volatile semiconductor memory device is characterized in that it has smaller area of cell occupation per bit as compared with an SRAM (Static Random Access Memory) that typically requires six transistors per memory cell, and that a refresh operation for holding data required in a DRAM (Dynamic Random Access Memory) is unnecessary. Storage of a large amount of data such as sound or image is required also for a non-volatile semiconductor memory device, and hence, increase in storage capacity thereof has been desired.
In such a non-volatile semiconductor memory device having large storage capacity, a construction is generally used in which the memory array is divided into a plurality of blocks, an X decoder and a Y decoder for selecting memory cells are arranged for each block, and memory cell selection is performed in a block basis. As only a selected block is operated, power consumption can be reduced. Further, the number of memory cells connected to a bit line can be reduced by such block division, and therefore, load of the bit line is reduced, achieving higher speed of accessing.
Such a construction of the non-volatile semiconductor memory device having large storage capacity is disclosed, for example, in “An Overview of Flash Architectural Developments”, PROCEEDINGS of the IEEE, Vol. 91, No. 4, April 2003, pp. 523-536.
As disclosed in the reference above, in a non-volatile semiconductor memory device, an address decode circuit (including a predecode circuit) is provided for each memory array block. An address signal applied in synchronization with an external clock signal is latched by an address latch circuit arranged commonly to the memory array blocks, predecoded and then, supplied to each address decode circuit.
In the non-volatile semiconductor memory device, a command designating an operation mode is supplied to an address input circuit through an address signal line. The address latch circuit is arranged on one end side of the memory array, in the vicinity of the address input circuit. Further, the predecode circuit is arranged on one end side of the memory array in the vicinity of the address latch circuit, in order to reduce the number of internal address signal lines and to reduce charging/discharging current of the internal address signal lines, and supplies a predecode signal to each address decode circuit. Therefore, when the memory array size increases as the storage capacity increases, the signal line transmitting the internal address signal from the address predecode circuit to each address decode circuit becomes longer to have an increased load. Consequently, the address predecode signal comes to have large skew, that is, difference in arrival time of address predecode signal becomes larger between the leading end and terminating end of the address predecode signal transmitting line. Accordingly, a margin for the timing of starting memory cell selection becomes smaller, making it difficult to guarantee accurate memory cell selecting operation. In order to ensure sufficient margin for the memory cell selecting operation and the data reading operation, it is necessary to set the timing of memory cell selection/data reading operation, taking into account the worst case of arrival of the address predecode signal to the address decode circuit, which makes it difficult to achieve a high-speed operation.
For accurate data reading, it is necessary to correct an erroneous bit if present. Provision of the error correction function (ECC function) improves efficiency in repairing a defective bit, and hence improves production yield. When the bit width of the internal read data increases to 64 bits or to 128 bits, the number of bits for error detection/correction must be increased for accurate error detection/correction.
When an error of the stored data is simply to be detected, an even/odd parity bit (s) is added, and typically, 1 bit of parity bit is added on the basis of 8-bit unit. In this case, whether there is an error or not can be detected, dependent on whether the least significant bit of the addition result value of the read out 8 bit data matches the parity bit or not. Parity check using even/odd parity bit (s) can detect an error while it cannot specify the bit that causes the error. Therefore, error correction is impossible. When an ECC code is used to realize the error detection/correction function, typically, an ECC code typically of 7 bits is added to the data of 64 bits. Here, information data and the ECC data must be read at the same speed, to perform error detection and correction. In the aforementioned reference, the manner how the data bit for error detection/correction is stored in the memory array and how the data bit and the ECC code bit are read substantially at the same speed to achieve high-speed reading are not at all considered.
In order to achieve high-speed data reading, it is necessary to initialize the internal circuitry at a timing as fast as possible, to be ready for the next reading cycle. Generally, a non-volatile semiconductor memory device operates in a static manner like an SRAM, for decoding an address and providing data output. In a large storage capacity memory, signal lines in the data reading path are of different length, propagation time of internal data differs dependent on the position of a selected memory cell, and hence the timing at which the data is made definite differs for each data bit in the data output circuit. Therefore, in this case also, in order to read data accurately, the data reading timing and the timing for initializing the data output path must be set considering the worst case. Therefore, the cycle time of data reading cannot be reduced, and it becomes difficult to achieve high-speed reading.